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An efficient hardware architecture for HMM-based TTS system

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This work proposes a hardware
architecture for HMM-based text-to-speech
synthesis system (HTS). In high speed
platforms, HTS with software core-engine
can satisfy the requirement of real-time
processing. However, in low speed
platforms, software core-engine consumes
long time-cost to complete the synthesis
process. A co-processor was designed and
integrated into HTS to accelerate the
performance of system.

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