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A Design of 10-b 100-MS/s Pipelined Folding ADC with Distributed Trackand- Hold Preprocessing

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This paper presents a 10-b ADC
designed in a 0.18-μm CMOS technology.
The ADC achieves 10-b resolution by using
the cascaded folding technique in both the
fine and coarse converters. Folding stages
are pipelined to improve the settling time. As
a result, this ADC can achieve the sampling
rate up to 100MS/s. Moreover, instead of
using a costly single track-and-hold circuit, a
distributed track-and-hold circuit is used to
reduce the chip area and the power
consumption. This also allows utilizing the
open-loop architecture of the folding
technique, thus improving the performance
of the system. The simulation results show
that with a 49 MHz sine-wave input, the ADC
consumes 66 mW and the effective number
of bit (ENOB) is 9.28-b. Taking into account
of process variations by using a Monte Carlo
simulation, the DNL varies from ±0.45LSB to
±0.25LSB. The layout of the ADC occupies
1.2 mm2 die area.

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