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A 6-bit Low-Power High-Speed Flash ADC using 180 nm CMOS process

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In this paper we present a design of
Flash-ADC that can achieve high
performance and low power consumption.
By using the Double Sampling Rate
technique and a new comparator topology
with low kick-back noise, this design can
achieve high sampling rate while still
consuming low power. The design is
implemented in a 0.18 m CMOS process.
The simulation results show that this design
can work at 400 MSps and power
consumption is only 16.24 mW. The DNL
and INL are 0.15 LSB and 0.6 LSB,
respectively.

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